Jayaprabhu R.

WORK HISTORY

EDUCATION

SKILLS

ABOUT JAYAPRABHU R.

Summary:I am a Master\'s student Graduated in Electrical Engineering from California State University, Sacramento. I share a good understanding of ASIC, SoC, System design, and verification using UVM, Formal Verification, SystemVerilog for assertions, RTL Design, Digital Logic Design and Synthesis, Pipelined Computer Architectures, out of order processors, Memories, through my coursework at CSUS. I strongly believe in Benjamin Franklin\'s saying:\"Tell me and I forget. Teach me and I remember. Involve me and I learn.\" I am seeking an involvement in Full-time opportunity in Digital/ASIC/SoC Hardware Design/Verification to learn, innovate and contribute towards the growth and development.Skills: •Proficiency: RTL Design, Static Timing Analysis, Test and Debug, Digital Logic Design, Timing Closure.•Languages: Verilog, VHDL, SystemVerilog, Perl, Python, C, C++. SVN, GIT. •Software Tools: Synopsys VCS, Design Vision, Vim, Proteus, Xilinx ISE, Multisim, DFT, Primetime, Cadence Virtuoso, PSpice, MATLAB, LabVIEW.•Bus Protocols: AMBA, APB, AHB, PCI, UART, PCIe, USB, SATA, SAS, MESI, Berkeley, Cache Coherency.•Methodology: UVM.•Other: CPU Design, ASIC and SoC design, Simulation & Verification of Design, Synthesis and Constraint development.•Operating Systems: Mac OS, Unix/Linux, Windows