Jayaprabhu R.

About Jayaprabhu R.

Summary:I am a Master\'s student Graduated in Electrical Engineering from California State University, Sacramento. I share a good understanding of ASIC, SoC, System design, and verification using UVM, Formal Verification, SystemVerilog for assertions, RTL Design, Digital Logic Design and Synthesis, Pipelined Computer Architectures, out of order processors, Memories, through my coursework at CSUS. I strongly believe in Benjamin Franklin\'s saying:\"Tell me and I forget. Teach me and I remember. Involve me and I learn.\" I am seeking an involvement in Full-time opportunity in Digital/ASIC/SoC Hardware Design/Verification to learn, innovate and contribute towards the growth and development.Skills: •Proficiency: RTL Design, Static Timing Analysis, Test and Debug, Digital Logic Design, Timing Closure.•Languages: Verilog, VHDL, SystemVerilog, Perl, Python, C, C++. SVN, GIT. •Software Tools: Synopsys VCS, Design Vision, Vim, Proteus, Xilinx ISE, Multisim, DFT, Primetime, Cadence Virtuoso, PSpice, MATLAB, LabVIEW.•Bus Protocols: AMBA, APB, AHB, PCI, UART, PCIe, USB, SATA, SAS, MESI, Berkeley, Cache Coherency.•Methodology: UVM.•Other: CPU Design, ASIC and SoC design, Simulation & Verification of Design, Synthesis and Constraint development.•Operating Systems: Mac OS, Unix/Linux, Windows

Experience

1. Senior Quality and Ci Engineer

   Shyft Global Services

   Nov 2024 — Present · Roseville, CA, US

Education

• SNS College of Technology

  Bachelor's degree, Electrical, Electronics and Communications Engineering

  2008 — 2011

• Nanjiah Lingammal Polytechnic College

  Associate's degree, Electrical, Electronics and Communications Engineering

  2007 — 2008

• California State University-Sacramento

  Master's degree, Electrical and Electronics Engineering

  2014 — 2017

Skills

• Management
• Engineering
• Networking
• Windows
• Verilog
• Pspice
• Microsoft Excel
• Powerpoint
• Cadence Virtuoso
• Matlab
• Public Speaking
• Python
• Unix
• Microsoft Word
• Tcl
• Autocad
• Leadership
• Research
• Assembly Language
• Systemverilog
• Application-Specific Integrated Circuits (Asic)
• Very-Large-Scale Integration (Vlsi)
• Perl
• Embedded Systems
• Html
• Fpga
• Embedded Software
• Testing
• Sql
• Linux
• Modelsim
• Design Verification Testing
• Team Management
• 8051 Microcontroller
• Vhdl
• Synopsys Tools
• Labview
• Negotiation
• Computer Architecture
• Project Planning