Sachin Jain
Logic Design Methodology Engineering at Intel Corporation
- Role
- Logic Design Methodology Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Sachin Jain
Semiconductor Industry | Expertise in Clock & Reset Domain Crossing Methodology | Working on VLSI FrontEnd TFMs | Verilog, SystemVerilog, Perl, Python, TCL | SpyGlass, VC-Static, VCS, Questa, Design Compiler, Fusion complier | Project Dashboards development | Learning Mixed Signal Design TFMsStrong engineering professional with a Master of Technology (M.Tech.) specialisation in VLSI Design from Nirma University & Bachelor of Technology (B.Tech.) in Electronics and Communication Engineering from Indus University.
Experience
Logic Design Methodology Engineer
Aug 2025 — Present · Bengaluru, IN
Education
Infocity Junior Science College,Gandhinagar
High School, Mathematics and Computer Science
2010 — 2012
Nirma University
Master’s Degree, VLSI
2016 — 2018
Indus University , Ahmedabad
Bachelor of Technology (BTech), Electronics & Communication
2012 — 2016
Sakar English School
Secondary Education, Social Sciences , Mathematics
2004 — 2010
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