Jai Nangia
- Role
- Senior Debug Lead - Soc Design at AMD
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
About Jai Nangia
As a Senior Debug Lead at AMD, I oversee the debug effort of critical issues seen during…
Experience
Senior Debug Lead - Soc Design
Mar 2021 — Present
Leading the debug effort of critical issues seen during chip bring-up and feature/power validation pertaining to memory (DDR5/LPDDR5/DDR4/LPDDR4) and high speed interfaces. • Overseeing system margining and feature validation activities and reporting analysis reports/conclusions to higher level forums • Collaborating with external vendors and reporting debug findings to external customers.
Skills
- Mixed Signal
- Verilog
- Verilog-Ams
- Computer Architecture
- Project Management
- Physical Design
- C++
- Vhdl
- Spice
- Hardware Design
- Intel
- Signal Integrity
- Pcie
- Processors
- Asic
- Perl
- Debugging
- Semiconductors
- Analog
- Simulations
- Cadence Virtuoso
- Functional Verification
- Unix
- Testing
- Spectre
- Circuit Design
- Electronic Engineering
- Serdes
- Cmos
- C
- Analog Circuit Design
- Soc
- Computer Hardware
- Engineering Management
- Programming
- Fpga
- Test Equipment
- Ic
- Sensors
- Matlab
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