Siddhartha Jain

About Siddhartha Jain

I’m a Senior CPU Design Engineer at Qualcomm, specializing in CPU RTL implementation, microarchitecture, and low-power digital logic design. With a strong foundation in computer architecture and extensive experience in SystemVerilog, Verilog, and EDA tools, I focus on building efficient, high-performance logic for next-generation CPU cores.At Qualcomm, I work on the Load/Store Unit (LSU), implementing and optimizing RTL for core logic components to improve overall CPU performance, power, and area (PPA). My expertise spans areas such as pipeline design, clock gating, and logic optimization, ensuring robust and scalable hardware architecture.Previously, I worked at Meta (via Accenture) and Intel, contributing to bus architecture design and FPGA-based verification projects.I’m deeply passionate about CPU architecture, RTL design, and power-efficient digital design, and I enjoy applying rigorous engineering discipline to deliver reliable, high-quality hardware solutions.

Experience

1. Senior Cpu Rtl Design Engineer

   高通

   Feb 2021 — Present · San Diego, CA, US

   Develop and validate CPU-core RTL designs as part of the Load/Store Unit (LSU) team.• Drive low-power microarchitecture improvements by identifying and implementing RTL-level clock gating and logicoptimizations to reduce dynamic power.• Collaborate with Physical Design and low-power architecture teams to optimize PPA (Performance, Power, Area)trade-offs.• Perform RTL quality checks including Lint, LEC, regressions, timing depth analysis, and power simulations to ensure functional correctness and validate power/timing savings before handoff.• Work closely with verification teams to maintain functional correctness during RTL updates.• Deliver ongoing power-efficiency enhancements in the LSU block, reducing CPU subsystem power while preserving functionality and timing closure.

Education

• Portland State University

  Master's in Electrical and Computer Engineering, VLSI Design Verification and Validation

  2018 — 2020

• Sandeepni School Of VLSI Design

  Internship In Design, VLSI: Digital Design, FPGA, Verilog, Scripting

  2018 — 2018

• Bharati Vidyapeeth's College Of Engineerin Pune

  Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering

  2010 — 2014

Skills

• Microsoft Office
• Microsoft Excel
• Powerpoint
• English
• Windows
• Microsoft Word
• Research
• Outlook
• Teaching
• Photoshop
• Public Speaking
• Have Basic Knowledge of Matlab , Keil , Xlinx Software
• Java
• Javascript
• Sql
• Html
• Jsp
• Xml