Jaimin Mehta
- Role
- Digital Design Engineer at Cirrus Logic
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
Experience
Digital Design Engineer
Aug 2014 — Present
Skills
- Dft
- Matlab
- Debugging
- Rf
- Static Timing Analysis
- Pll
- Phase-Locked Loop (Pll)
- Systemverilog
- Soc
- Rtl Coding
- Rtl Design
- Asic
- Ic
- Verilog-Ams
- Circuit Design
- Logic Synthesis
- Verilog
- Mixed Signal
- Timing Closure
- Transceivers
- Digital Signal Processing
- Primetime
- Digital Communication
- Signal Processing
- Dsp
- Cmos
- Vhdl
- Semiconductors
- Ofdm
- System on a Chip (Soc)
- Fpga
- Rtl Verification
- Wireless Communications Systems
- Integrated Circuit Design
- Vlsi
- Algorithms
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