Jaikumar A L

Experience

1. Senior Staff Engineer Manager

   Qualcomm

   Oct 2012 — Present · Bangalore, IN

   Works with Analog/Serdes/IOs/DDR team.Responsibilities- Involved in analog design/development activities of leaf cells and biasing circuits for Transceivers- Analog verification and characterization of - Multimedia PHYs: CSI, DSI, HDMI, eDP/DP. Peripheral PHYs :PCIe(Gen3/4/5), UFS, USB3/USB4, SGMI and RF/MDM linking PHYs. Also on characterizing MSIPs like ADC, DAC, PLL, DLL, CDC etc- Analog.libs cap/timing/power/Noise characterization. Worked closely with physical design team to meet the timing @ digital-analog interface of high speed SerDes IPs- Functional verification of SerDes analogs @ different data rates- Leakage analysis : For different power states like PoR, ATPG, FreezeIO, Sleep_B and HiZ,JTAG/BSCAN modes for all SerDes IPs. Worked closely with global DV, DA and AD teams- IR/EM/Thermal sign off : Transistor level Signal, Power IR/EM sign off using Totem. Worked closely with Layout engineers to fix possible grid weakness, missing vias, reliability issues etc- RH - Physical and Electrical (APL) views support for PD for their IP level IR/EM analysis- ESD sign off : B2B, CD analysis. RVDD, RVSS fix to avoid possible IC damage during to ESD events- MvS certification : Cell certification of leaf cells, analog macros and multiple analog libraries- On Die Decap Extraction: Intrinsic, intentional and PG caps from all IPs to avoid power noise in PDN simulations- Have an experience working with cross functional teams – AD, DD, DV, Layout, PD,PSD and PDN teams and tool vendors (Synopsys, Ansys, Siemens and Cadence)- Leading the team of 10+ engineers in the analog verification and characterization activities. EDA TOOLS - Cadence® Virtuoso XL ADEL/ADEXL, Layout editor- Hspice, Spectre, AFS, Finesim and XA simulators- WaveViewer- SiliconSmart- Calibre(LVS/DRC), StarRC/XACT(Extraction)- Totem/Redhawk/PathFinder/Pgx- Ansys Utilities - ACE/gds2def/Sim2Iprof/Aqua/Aplreader etc

Education

• Birla Institute of Technology and Science, Pilani

  Master’s Degree, Microelectronics

  2013 — 2015

• Bharathi pre university college, Bharathi nagar

  PUC, PCMB

  2004 — 2006

• Sri Jayachamarajendra College of Engineering , Mysore

  BE, Electronics and communication

  2006 — 2010

Skills

• Hardware Architecture
• Perl
• Silicon Smart for Standard Cell Characterization.
• Spectre
• Shell Scripting
• Logic Design
• Mixed Signal
• Tcl
• Analog
• Cadence Skill
• Cadence Virtuoso
• Vlsi
• Cmos
• Lvs
• Ultrasim