Jaiganesh Raman

About Jaiganesh Raman

With over 15 years in the semiconductor industry, I’ve led cross-GEO, cross-functional teams through the kind of fast-moving, ambiguous environments where clarity is rare and context-switching is basically a full-time job. I’ve worn many hats — tech lead, product owner, product manager, people manager, occasional chaos coordinator — sometimes all on the same day.I’ve guided initiatives requiring alignment across orgs, technologies, teams, and time zones — all without losing sight of the people at the heart of it all.In early-stage advanced process node development, instability is the default setting. I specialize in taming messy tool flows, processes, and collaterals, turning them into stable, scalable systems that designers can actually trust. I’ve built products from scratch, improved the efficiency of existing systems, and streamlined workflows that previously ran on caffeine and optimism.I bring deep experience in both transistor-level and cell-level static timing analysis (STA), building robust STA infrastructures and standardizing methodologies across projects and process nodes. My goal is to eliminate ambiguity, reduce manual overhead, and ensure teams spend less time debugging the flow — and more time actually designing. My north star? Make life easier for the user: accurate flows, fewer crashes, less yelling at screens.What excites me most? Building systems that work — whether they’re technical, organizational, or operational. I love turning ambiguity into alignment and inefficiency into momentum. Whether it’s stabilizing early-node environments or managing multiple products across multiple process technologies, I find joy in bringing order to moving targets.Success for me is about delivering value, enabling scale and building high-performing teams and I measure it by how often someone says \"Wow, that actually works now\'.

Experience

1. Digital Design Automation & Methodology Engineering Manager

   Intel

   Jun 2022 — Present

Education

• Arizona State University

  MSE

  2008 — 2010

• Birla Institute of Technology and Science, Pilani

  B.E.(Hons)

  2004 — 2008

Skills

• Spice
• Verilog
• Circuit Design
• Asic
• Vlsi
• Modelsim
• Vhdl
• C++
• Tcl
• Functional Verification
• Integrated Circuit Design
• Cadence
• Systemverilog
• Perl
• Cadence Virtuoso
• C
• Rtl Design
• Static Timing Analysis