Jaidev Kaushik
Senior Physical Design Engineer
- Role
- Senior Physical Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Jaidev Kaushik
Experienced Physical Design Engineer | APR | Place & Route | AI-Driven PNRWith 6 years of experience in physical design, I specialize in automated place & route (APR), scripting, and optimizing cutting-edge semiconductor designs. My expertise lies in full-chip physical implementation, from floorplanning to tapeout, ensuring high-performance and power-efficient designs.Passionate about integrating AI-driven automation in PNR, I leverage scripting and ML techniques to enhance efficiency, reduce turnaround time, and push the boundaries of design automation. My goal is to bridge the gap between traditional ASIC design methodologies and AI-powered innovations to create next-generation silicon solutions.Having hands on experience of working on super fine node 18A along with all cutting edge tech node 3nm, 5nm, 7nm and 10nm. Key Skills: APR (Place & Route)| Floorplanning | CTS | Routing | Timing Closure Scripting (Tcl, Python, Perl) for automation & efficiency AI/ML applications in Physical Design
Experience
Senior Physical Design Engineer
Jun 2019 — Present · Bengaluru, IN
Bengaluru, Karnataka, India
Education
Punjab Technical University
Master of Technology - MTech
2013 — 2016
Skills
- Microsoft Word
- Tcad
- Powerpoint
- Microsoft Excel
- Leadership
- Very-Large-Scale Integration (Vlsi)
- Photoshop
- Arteries
- Html
- Customer Service
- Microsoft Office
- Windows
- Research
- C
- Matlab
- C++
- Verilog
- Vlsi Cad
- Adobe Photoshop
- Cadence Virtuoso
- Public Speaking
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.