Jaideep Singh Gour
ASIC design - Static Timing Analysis | Timing closure | Physical design
- Role
- Staff Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Jaideep Singh Gour
Jaideep Gour Contact Details : j••••••••@gmail.com,+91••••••••68Physical Design Engineer competent in Timing Closure and Constraints Development with 12+ years of experience in the Semiconductor Industry. Successfully performed and handled full-chip and block-level Static Timing Analysis for multiple SoC and strengthened STA methodologies to achieve Quality closure and on-time execution
Experience
Staff Engineer
Jun 2025 — Present · Bengaluru, IN
I am looking at Timing closure related activities for intel core, a very high frequency design at 14A
Education
Arizona State University
Master of Science (M.S.), Computer Engineering
2015 — 2016
National Institute of Technology, Tiruchirappalli
Bachelor of Technology (B.Tech.), Electrical and Electronics Engineering
2006 — 2010
Skills
- Unix Shell Scripting
- Perl
- Very-Large-Scale Integration (Vlsi)
- Microcontrollers
- Signal Integrity
- Static Timing Analysis
- Linux
- Verilog
- C
- Matlab
- Omap
- Problem Solving
- C++
- Vlsi
- Rtl Coding
- Parasitic Extraction
- Simulations
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