Jaideep Patel

About Jaideep Patel

Final-year B.Tech (ECE) student at Manipal University Jaipur, actively pursuing a VLSI internship in RTL Design or SoC Verification. I specialize in Verilog/SystemVerilog, UVM, and hardware automation using industry-standard tools like Vivado, ModelSim, and Active-HDL. Built and verified multiple IPs: UART with UVM testbench (91.3% coverage, error injection, loopback) AHB to APB Bridge using FSM-controlled RTL design Low-power FSM with Clock Gating All projects are documented and published on GitHub with waveforms and testbench automation using TCL/PowerShell. Also built an ML-powered CMOS VDD prediction tool using Python + Streamlit, blending EDA and data science. Core Skills: RTL Design · Functional Verification · UVM · Assertions TCL/Python/Shell · Simulation Automation · GitHub Projects Protocols: UART, AHB/APB, AXI (basic) · CMOS Analysis Goal: Actively seeking a VLSI Design or Verification internship (Jul–Aug 2025) in semiconductor or EDA companies working on RTL, SoC, or DFT workflows. Open to VLSI internship roles across India, with a preference for Bangalore, Hyderabad, or Pune. Eager to contribute to IP development, testbench creation, and coverage closure in a fast-paced hardware team. Let’s connect if you\'re hiring, mentoring, or collaborating in the semiconductor domain.

Experience

1. Vlsi Design Intern

   Maven Silicon

   Jun 2025 — Present

Education

• Manipal University Jaipur

  Bachelor of Technology - BTech

  2022 — 2026

• St. Anne's School Jodhpur

  Science