Jai Verma
Sr Asic Engineer @NVIDIA
Santa Clara, CA, US
EMAILS
MOBILE NUMBERS
+15•••••••68
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WORK HISTORY
Jan 2025 — Present
Sr Asic Engineer @NVIDIA
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EDUCATION
2003 — 2008
Indian Institute of Technology, Kanpur
B-Tech/M-Tech, Electrical Engineering
2008 — 2013
University of Notre Dame
M.S; PhD, Electrical Engineering
2003 — 2008
IIT KANPUR
M.Tech, Electrical Engineering
2003 — 2008
IIT KANPUR
B.Tech, Electrical Engineering
SKILLS
TemAfmPhysicsNanotechnologyCmosPhotolithographyNanofabricationMaterials ScienceThin FilmsMathematicaCCharacterizationScanning Electron MicroscopyElectron Beam LithographyMbe Growth, Fabrication, Tem Characterization
ABOUT JAI VERMA
System Validation Methodology Engineer
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