Jai Prakash Sharma

About Jai Prakash Sharma

20+ years of experience of working with top semiconductor companies like Intel, Freescale and Qualcomm, resulting to all-layer Tape-Out of multiple complex, multi-million gate SOCs in various technology nodes. Have extensive hands-on expertise & leadership experience in converging and signing off full-chip flat & hierarchical EMIR (PDN and RV) closure, PDN strategy & methodology development to converge FOVEROS SOCs, Silicon desegregation methodologies to converge multi chiplet based Foveros SOCs. Played a technical expert role in post-si power delivery quality measurements and pre-si correlation. Presently working with Intel India, Bangalore, and managing and technically leading a team of highly skilled engineers for the PDN/Reliability/ESD/analog IP integration convergence and signoff. Technical and leadership expertise : • PDN (Power Delivery Network, EM IR,ESD) signoff and convergence for monolithic/ 3DIC/ 2.5D SOCs• Post Silicon PDN noise analysis and debug• Post Silicon AC and DC load line characterizations of SOC rails• Setup and formed a team of fresh engineers, helped them to ramp up quickly and executed complete platform architecture and platform level power delivery solution for two test chips

Experience

1. Director of Engineering

   Intel

   Jul 2025 — Present · Bengaluru, IN

Education

• Kurukshetra University

  B.tech, Electrical Engineering

  1996 — 2000

• Thapar Institute of Engineering & Technology

  Master’s Degree, VLSI design and CAAD