Jagvinder Yadav
Principal Engineer, R&D at Synopsys Inc.
- Role
- Principal Engineer at 新思科技股份有限公司
- Location
- Gurugram, HR, IN
- LinkedIn followers
- 500 followers
About Jagvinder Yadav
20+ Years of Experience in Verification IP (VIP) Architecture, Development, Functional Verification domain using System Verilog, System-C, Specman \'e\', Verilog and Industry proven methodologies (UVM-SV, VMM, OVM, uRM, eRM).Involved in VIP development for various protocols including HDMI 2.1/2.0/1.4/1.3, HDCP 2.2/1.4, DDR4 NVDIMM-P, MHL3.0, I2C, SAS, SAS-12G, SATA, PCIe, USB 3.0, JPEG Ethernet Switch, Gigabit Ethernet (GbE).
Experience
Principal Engineer
Feb 2025 — Present · Noida, IN
Education
Raj Rishi Bhartrihari Matsya University (RRBMU), Alwar
Bachelor of Laws - LLB
2016 — 2020
CDAC
CDAC, PG Diploma in VLSI Design
2005 — 2006
Apeejay College Of Engineering
B.E., Electronics and Instrumentation Engineering
2001 — 2005
Saraswati Senior Secondary School
Physics, Chemistry, Maths, English
1996 — 2001
Skills
- Asic
- Universal Verification Methodology (Uvm)
- I2c
- Eda
- Specman
- Usb3.0
- Functional Verification
- Debugging
- Rtl Verification
- Sas
- Modelsim
- Open Verification Methodology
- Formal Verification
- Vlsi
- Vmm
- Usb
- Ncsim
- Verilog
- Arm
- Ethernet
- Rtl Coding
- Pcie
- Timing Closure
- Systemverilog
- Sata
- Uvm
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.