Jagriti J.
Silicon Packaging Design Engineer at Intel Corporation | Advanced Packaging | Substrate Design | SI/PI | 2.5D/3D Integration | IIT Patna
- Role
- Silicon Packaging Design Engineer at Intel
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Jagriti J.
I’m a Silicon Packaging Design Engineer with over 6 years of experience at Intel. My…
Experience
Silicon Packaging Design Engineer
Sep 2020 — Present · IN
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