Jagriti J.

Silicon Packaging Design Engineer at Intel Corporation | Advanced Packaging | Substrate Design | SI/PI | 2.5D/3D Integration | IIT Patna

Role
Silicon Packaging Design Engineer at Intel
Location
Bengaluru, IN
LinkedIn followers
500 followers

About Jagriti J.

I’m a Silicon Packaging Design Engineer with over 6 years of experience at Intel. My…

Experience

  1. Silicon Packaging Design Engineer

    Intel

    Sep 2020 — Present · IN

Find verified contacts for anyone on LinkedIn

Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.

Free plan included · No credit card required

This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.

Jagriti J. — Silicon Packaging Design Engineer at Intel in Bengaluru, IN | Unifers