Jagdish Mohapatra
Hardware Engineer @Meta (previously Rivos, Nvidia, Qualcomm) | UW-Madison
- Role
- Silicon Engineer at Meta
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
About Jagdish Mohapatra
Recently joined Meta in the Meta Training & Accelerator(MTIA) division. Previously worked as CPU fabric μArchitect at Rivos, contributing to the development of next-generation on-chip interconnects and NoCs. Expertise spans Out-of-Order CPU backend microarchitecture, CHI protocol based on-chip coherent fabric interconnects/NoCs, familiarity with AXI, CHI protocols & protocol bridges/converters and operating systems. With industry experience at Qualcomm, NVIDIA, Rivos and academic grounding from the University of Wisconsin-Madison, I am driven to push the boundaries of CPU and accelerator load-store-unit, L2-cache, last level cache (LLC), coherent and non-coherent on-chip fabric/interconnect designs.
Experience
Silicon Engineer
Jan 2026 — Present · Sunnyvale, CA, US
Education
Indian Institute of Technology, Madras
MTech - Master of Technology, Microelectronics and VLSI Design
University of Wisconsin-Madison
Master of Science - MS, Computer Engineering
2021 — 2023
Silicon Institute of Technology (SIT), Bhubaneswar
Bachelor of Technology - BTech, Electronics
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