Jagdish Agrawal

About Jagdish Agrawal

More than 23 years of total experience in digital design of mixed signal projects, experience in concept design, micro-architectural design, DSP reference models in MATLAB, Filter designs in MATLAB, RTL coding, logic design, behavior coding, synthesis, static timing analysis, scan insertion, functional verification, datapath-intensive verification, post processing and bit to bit comparison against MATLAB models, UVM based verification, circuit simulation, layout verification, back annotation and test program development. Complete knowledge and hands on experience of entire ASIC design flow·Completed projects in the communication space and very high speed and complex digital logic for RF DACs/ADCs. ·Went through many successful project cycles in 28nm, 45nm, 65nm and other geometries process. And successfully played the pivotal role for multimillion gate chips. Includes the first time silicon success for various chips.·Individually contribution has been more on the front end design i.e. specification finalization, feasibility study, micro architecting the chip, RTL design, functional verification planning, and execution. Analog interface block design, handling timing related interface issues, Post PNR STA and dynamic simulation.

Experience

1. Design Manager

   Texas Instruments

   Jul 2017 — Present · Bengaluru, IN

Education

• Motilal Nehru National Institute Of Technology

  BE, EnT

  1992 — 1996

Skills

• Embedded Systems
• Eda
• Rtl Design
• Soc
• Mixed Signal
• Static Timing Analysis
• Verilog
• Cmos
• Ic
• Asic
• Integrated Circuit Design
• Vlsi
• Analog