Jagannath Sadasivam
Sr. RTL Design Engineer at Amazon Lab126
- Role
- Sr Rtl Design Engineer at Amazon Lab126
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Jagannath Sadasivam
1) Memory sub-system design for Amazon Alexa SoCs2)ASIC design and architecture for Nvidia GSYNC gaming monitors.3) RTL IP design (Video Decoder, Ethernet MAC).
Experience
Sr Rtl Design Engineer
Jul 2018 — Present · Sunnyvale, CA, US
Education
National Institute of Technology Karnataka
Bachelor of Engineering, Electronics and Communication
2002 — 2006
UCLA
Masters, Electrical Engineering
2010 — 2012
MES College
Pre University Certificate, Science
2000 — 2002
Skills
- Logic Design
- Cadence Virtuoso
- Rtl Design
- Synopsys Primetime
- High-Speed Digital Design
- Gsync
- C
- Perl
- Xilinx
- Verilog
- Modelsim
- Application-Specific Integrated Circuits (Asic)
- Digital Electronics
- Synopsys Tools
- Synplify Pro
- Vhdl
- Simulations
- System on a Chip (Soc)
- Field-Programmable Gate Arrays (Fpga)
- Soc
- Hardware Architecture
- Fpga
- Asic
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