Jagannath Kanireddy
Layout Design Engineer at Capgemini engineering
- Role
- Layout Design Engineer at Capgemini Engineering
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Layout Design Engineer
Jan 2022 — Present · Bangalore Urban, IN
Education
Cmr Institute of Technology
Bachelor's Degree
2009 — 2012
Skills
- Static Timing Analysis
- Drc
- Pnr
- Cadence Virtuoso
- Physical Verification
- Design Rule Checking (Drc)
- Layout Versus Schematic (Lvs)
- Logic Synthesis
- Very-Large-Scale Integration (Vlsi)
- Lvs
- Encounter
- C
- Microsoft Office
- Vlsi
- Cmos
- Physical Design
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