Jagan J.
FPGA Engineer
- Role
- Asic Design and Fpga Verification Engineer at Rajant Corporation
- Location
- Phoenix, AZ, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Jagan J.
FPGA Engineer with extensive experience in digital design doing SoC, IP design, FPGA and chip validation tasks.
Experience
Asic Design and Fpga Verification Engineer
Aug 2022 — Present
Education
St. Thomas Residential School
High school
1994 — 2003
College of Engineering Trivandrum
Bachelor of Technology, Applied Electronics and Instrumentation
2003 — 2007
Arizona State University
Masters in Electrical Engineering, Electronic and mixed-signal circuit design
2011 — 2013
Skills
- Matlab
- Shell Scripting
- Spyglass
- Finacle
- Toad
- Lint
- Cadence Virtuoso
- C/C++
- Linux
- Modelsim
- Vlsi
- Serial Peripheral Interface (Spi)
- Python
- Latex
- Verilog
- Oracle Sql
- Brio Query
- Eclipse
- Peoplesoft
- Spi
- C++
- Database Management
- Mysql
- Unix
- Opengeo Suite
- C
- Cdc
- High Speed Usb Controller
- Hyperion
- Unix Shell Scripting
- Pl/Sql
- Oracle
- Systemverilog
- Usb2.0 Controller Design (Usb)
- Simulink
- Usbcontrollerdesign
- Cadence Spectre
- Perl
- Testing
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.