Jagadish Rongali
- Role
- Senior Principal Engineer at NXP Semiconductors
- Location
- Irvine, CA, US
- LinkedIn followers
- 500 followers
About Jagadish Rongali
Engineering professional with 15+ Years of Experience in ASIC/FPGA Design Verification,…
Experience
Senior Principal Engineer
Oct 2022 — Present
Education
Jawaharlal Nehru Technological University
B.Tech, Electrical and Electronics
2001 — 2005
Indian Institute of Technology, Bombay
M.Tech, Systems and Control Engineering
2005 — 2007
Skills
- Axi
- Microprocessors
- Sta
- Vhdl
- Device Drivers
- Testing
- Dft
- Asic
- Eda
- Vlsi
- Logic Synthesis
- Static Timing Analysis
- Debugging
- Rtl Design
- Xilinx
- Pcie
- Fpga
- Semiconductors
- Altera
- Ddr
- Perl
- Timing Closure
- Modelsim
- Rtl Coding
- Verilog
- Sdh
- Simulations
- Ddr2
- Uvm
- Systemverilog
- Embedded Systems
- Ncsim
- Python
- Processors
- Soc
- Arm
- C
- Functional Verification
- Tcl
- Emulation
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