Jagadish Bvn
Design Engineer
- Role
- Sr Principal Design Engineer at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Sr Principal Design Engineer
Sep 2025 — Present · Bengaluru, IN
Education
Pondicherry University
Bachelor of Technology (BTech), Electrical, Electronics and Communications Engineering
2005 — 2009
Skills
- Static Timing Analysis
- Dfm
- Routing
- Asic
- Timing
- Integrated Circuit Design
- Very-Large-Scale Integration (Vlsi)
- Sta
- Debugging
- Application-Specific Integrated Circuits (Asic)
- Soc
- Physical Design
- Vlsi
- Floorplanning
- First Encounter
- Lvs
- Ic
- Drc
- Tcl-Tk
- System on a Chip (Soc)
- Placement
- Primetime
- Vhdl
- Perl
- Embedded Systems
- Eda
- Verilog
- Timing Closure
- Tcl
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