Jagadesh Veerasamy

Module Development Engineer @Intel

OR, US

Sustained manufacturing equipment through consistent maintenance, exceeding factory KPI targets.• Developed robust electroplating processes, enabling TSV technology for Intel products like Meteor Lake and Arrow Lake.• Collaborated with cross-functional teams to develop electroplating process for high aspect ratio TSVs and TDVs.• Performed root cause analysis and designed experiments to debug inline defects like voids and delamination. • Defined and implemented FDC methodologies to monitor process quality and reduce process variability across technology nodes.• Evaluated different copper plating chemistries to characterize their effects on grain boundaries, interfacial sliding, electromigration and field uniformity.• Utilized PCSA and SPC strategies to monitor and identify continuous improvement initiatives to enhance overall process quality.• Served as the primary liaison for module ISO compliance and process documentation.• Designed and delivered equipment sustaining training programs for junior engineers and technicians across shifts• Led automation initiatives that reduced tool downtime by 15%, saving 200 man-hours and enhancing factory manufacturing availability.• Leveraged tool sensor data to deploy a predictive maintenance model, characterizing manufacturing equipment failures.• Collaborated on a virtual metrology initiative to predict TSV copper fill health and reduce inline test wafer consumption. • Evaluated and restructured preventive maintenance protocols, reducing human errors and equipment downtime.• Led cost reduction initiatives through vendor negotiations and spare parts evaluation, enhancing operational efficiency and driving overall performance improvements.• Authored and maintained process sustaining specifications for scalability and global transfer to HVM sites.