Jagadeesh Padi
- Role
- Senior Design Engineer at NVIDIA
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Jagadeesh Padi
Completed M.Tech Program in Department of Electronic Systems Engineering(formerly CEDT)…
Experience
Senior Design Engineer
Sep 2019 — Present
Implementing clocking for memory sub-system and uphy in Tegra chips.\\\\n- Functional/DFT/Physical clocking for next gen Tegra chips.\\\\n- Understanding clocking and reset aspects at system level.
Skills
- Leadership
- Project Management
- Embedded Systems
- Microsoft Office
- Microsoft Excel
- Management
- Microsoft Word
- Research
- Powerpoint
- Public Speaking
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