Jagadeesh K
A&MS layout design Engineer at Synopsys Inc
- Role
- a & Ms Layout Design Engineer at Synopsys Inc
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Jagadeesh K
VLSI, back-end layout (memory) and physical design
Experience
a & Ms Layout Design Engineer
Apr 2019 — Present · Hyderabad, IN
Education
Coventry University
Master's, VLSI System Design
2008 — 2010
Skills
- Hardware
- Physical Design
- Static Timing Analysis
- Fpga
- Asic
- Modelsim
- Verilog
- Rtl Verification
- Rtl Design
- Integrated Circuit Design
- Soc
- Debugging
- Systemverilog
- Vhdl
- Pcb Design
- Vlsi
- Functional Verification
- Perl
- Eda
- Tcl
- Layout
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