Jagadeesh B R
- Role
- Pre Silicon Verification Engineer at Intel
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Jagadeesh B R
Highly experienced ASIC verification engineer in verifying complex designs at the SoC…
Experience
Pre Silicon Verification Engineer
Oct 2019 — Present
Skills
- Testing
- C
- Pcie
- Rtl Design
- C++
- Systemverilog
- Perl
- Mipi Mphy
- Mpcie
- Verilog
- Ovm
- Veritas Cluster Server
- Functional Verification
- Modelsim
- Vhdl
- Vlsi
- Open Verification Methodology
- Ncsim
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