Jagadeesan M
post silicon validation| Artificial Intelligence and machine learning|Imaging|Graphic validation|NPU validation|ONNX,Pytorch framework|DML|GEN-AI
- Role
- Senior Validation Engineer at UST
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Jagadeesan M
I bring 9+ years of experience in manual testing, system validation, and debug across…
Experience
Senior Validation Engineer
Jun 2020 — Present · Bengaluru, IN
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