Jaee Bonde
CPU Design Verification Engineer at Intel Corporation
- Role
- Cpu Design Verification Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Jaee Bonde
Profound knowledge of Hardware Description Language Verilog,Digital IC design and low…
Experience
Cpu Design Verification Engineer
Sep 2023 — Present · Bengaluru, IN
Education
VIT University, Vellore, Tamilnadu, India
Master's Degree
2014 — 2016
Sant Gadge Baba Amravati University
Bachelor's Degree
2009 — 2013
Skills
- Cadence Virtuoso
- Lvs
- Perl
- Cadence
- Linux
- Modelsim
- Mixed Signal Ic Design
- Drc
- Digiatl Ic Design
- Microsoft Excel
- Cad Vlsi
- Integrated Circuit Design
- Microprocessors
- Tcl
- Microprocessor
- Analog Ic Design
- Scripting
- Microsoft Office
- Vlsi
- Cadence Encounter
- Vivado Tool
- Windows
- Verilog
- Very-Large-Scale Integration (Vlsi)
- Rtl Design
- Microcontrollers
- Fpga
- Asic
- C
- Soc
- Low Power Ic Design
- System on a Chip (Soc)
- Digital Ic Design
- Timing
- Quartus Ii
- Static Timing Analysis
- Digital Electronics
- Cadence Virtuoso Layout Editor
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