Jae Ho Lee

About Jae Ho Lee

Global Product Support (GPS) Process and Productivity Engineer: with etch expertise in process, product development, technology transfer to onsite, customer relation and onsite supportPlasma etch expert: Bevel etch and Bevel deposition product (productivity, process), Conductor etchProduct owner for multiple customer sitesResponsible for customer beta site activities: including installation, qualification, milestones, technical requirements, training and certification of local teams and customerMultiple CIP development technical owner Strong fundamental understanding of solid-state physics, device physics, memory device, and CMOS architectures (FEOL, BEOL), as well as diverse array of research and practical experiences in fabrication, nano material synthesis, and device characterization of semiconductor industryCreative thinker who is willing to challenge the status quo and work diligently toward common goals of the projectSemiconductor: Etch process development; Strong academic background on semiconductor material, device physics (CMOS, Flash, LED), fabrication, design, characterization; and Industry experience (etch, package). Etch process applications: FinFET, STI, metal gate, MO,Product selection, business perspective, customer follow up, customer support, customer experience, product development, BOM, procedure, project management, written communication, Energy: Li-ion battery, solar cell, fuel cell.Nano material: nanowire, carbon nanotube, nanofiber.

Experience

1. Global Product Support (Process, Productivity)

   Lam Research

   Jan 2021 — Present · San Francisco, CA, US

   Global Product Support.TSV HBM, BVR, Plasma dicing, deep Si etch, process development, productivity resolution.Metal etch, Conductor etch, Bevel Etch, MWS, and 150-200mm legacy tools: process development and productivity support

Education

• Rutgers University

  Master's degree, Electrical and Computer Engineering

  2003 — 2005

• Chungbuk National University

  Master's degree, Semiconductor Engineering

  1997 — 1999

• Chungbuk National University

  Bachelor's degree, Semiconductor Engineering

  1993 — 1997

• University at Albany

  Doctor of Philosophy (Ph.D.), Nanoscale Science and Engineering

  2005 — 2011

• University at Albany

  Master's degree, Nanotechnology

  2005 — 2008

Skills

• Silicon
• Materials
• Electroless Plating
• Electronics
• Design of Experiments
• Sputtering
• Research Software: Origin, Layout Editor, Intellisuite, Pspice, Comsol Multiphys
• Cvd
• Cmos
• Powder X-Ray Diffraction
• Xrd
• Thin Films
• Xps
• Tem
• Afm
• Dielectrophoresis
• Physics
• Eds
• Rbs
• Process Simulation
• Nanotechnology
• Plasma Etch
• Clean Room Facilities
• R&D
• Sem
• Scanning Electron Microscopy
• Aes
• Dual Beam Fib
• Engineering
• E-Beam Evaporation
• Semiconductors
• Characterization
• Spectroscopy
• Raman
• Pvd
• Probe Station
• Fib
• Materials Science
• Semiconductor Parameter Analyzer (Hp, Agilent, and Keithley)