Jacob Chang
Director of Engineering - Verification Formal Verification and Methodology @SiFive
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WORK HISTORY
Director of Engineering - Verification Formal Verification and Methodology @SiFive
Director of Engineering - Verification/Formal Verification and Methodology – Oct 2018 - Present Verification/Formal Verification and Methodology – Aug 1, 2016 - Sept 2018 Lead in verification infrastructure development to support automated testing of multiple designs variants in order to support delivery of ~20 customer designs/week Technical Lead • Formal Verification framework in Chisel Managerial Lead • Automated test plan generation • DPI-based memory model Lead verification effort to drive various multi-core RISC-V CPU design to completion Designs include three families of processors: • embedded processors, pipelined processors, and superscalar processors Technical Lead • ECC verification • TileLink unit level Formal Verification • Coverage closure - Developed cover property capability in Chisel • CDC / Lint Managerial Lead • Core verification - Random instruction generator - Privilege mode verification - Virtual memory verification - Physical memory protection verification - SiFive custom extension verification - Load store unit Formal Verification - Core pipeline Formal Verification - RISC-V vector extension • Memory system verification - On-chip memory network - Cache coherency • Uncore verification - Interrupt and interrupt controller verification - Debug unit verification • SystemC modeling • Regression infrastructure - Triage - License usage tracking + purchase of tools
EDUCATION
University of California, Berkeley
BS, Electrical Engineering and Computer Science / Engineering Physics
Stanford University
MS / PhD, Electrical Engineering
ABOUT JACOB CHANG
Director of Engineering - Verification
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