Joison Jacob
Sr. Professional II
- Role
- Sr Professional Ii at Capgemini Engineering
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Joison Jacob
Experience in ASIC Design flows, notably in Design Verification.Key Areas: Assertions, Coverages, Checkers, Constrained Random Verification Env\'s, BFM\'s, Transactions(TLM\'s Based), Integration and Configuration of VIP\'s at Subsystem and SOC level.Goals: Expertise in ASIC Design Verification with SV and its Methodologies, Arch and System Modelling, HW/SW Co-Verification, UVM-MS Simulation.Protocols Connectivity : PCIe, USB, JESD204C, SPI, I2C Bus : ACE, AXI, AHB, APB.HVL\'s and Methodologies: SystemVerilog, SystemC, Verilog HDL,VHDL UVMScripts: PerlTools: ncsim, vcsi, qvsim, IMC, Certitude, SCLive, iverilog-Icarus Verilog
Experience
Sr Professional Ii
Aug 2015 — Present
Education
Mar Augusthinose College
Bachelor’s Degree, Electronics and Computer Hardware
2002 — 2005
St.Joseph's College
Master’s Degree, Electronics
2005 — 2007
Sathyabama University
Master of Technology (MTech), VLSI Design
2007 — 2009
Skills
- Usb
- Bus Interface Protocols
- Verilog
- System Verilog
- Ovm
- Amba
- Vhdl
- Systemc
- Uvm
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