Jack Marshall
- Role
- Cadence
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
About Jack Marshall
Big-picture digital design engineer with experience in front end RTL design, physical…
Experience
Present
Education
University of Southern California
MSEE, Computer Engineering and Digital Signal Processing
University of Illinois Urbana-Champaign
BSEE, Digital Design
Skills
- Tcl
- Teaching
- Test Design
- Rtl Design
- Asic
- Application-Specific Integrated Circuits (Asic)
- Eda
- Primetime
- Fpga
- Mixed Signal
- Integrated Circuit Design
- Logic Synthesis
- Soc
- Debugging
- Static Timing Analysis
- Functional Verification
- System on a Chip (Soc)
- Verilog
- Cadence
- Rtl Coding
- Low-Power Design
- Field-Programmable Gate Arrays (Fpga)
- Integrated Circuits (Ic)
- Semiconductors
- Logic Design
- Ic
- Vhdl
- Very-Large-Scale Integration (Vlsi)
- Arm Architecture
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