Jabez James

About Jabez James

I’m a Product Engineer with 5+ years of experience in semiconductor manufacturing, ATE-compatible test development, and new product introduction (NPI) for high-speed CMOS image sensors and mixed-signal silicon systems.At Luxima Technology, I lead end-to-end test infrastructure development and package-level integration for advanced CIS devices. I’ve owned NPI execution for 5+ semiconductor products, including test system and socket development, wafer-level probe setup with OSAT partners, and yield ramp-up through RCCA and KPI-driven analysis. These efforts enabled a 2× test throughput increase, over $2M in cost savings, and >50% yield improvement across multiple product lines.My role spans DFM/DFT design review, sensor assembly and test development, and bring-up validation using FPGA-based platforms. I’ve also implemented automated monitoring solutions in MATLAB to support real-time data analysis and quality feedback loops during production.Fluent in SPC, DOE, and ATE-aligned test system design, I operate at the intersection of mechanical design, sensor reliability, and semiconductor production scale-up- Let’s connect if you work on silicon testing, ATE platforms, sensor validation, or quality engineering in advanced hardware systems.

Experience

1. Product Engineer

   Luxima Technology Llc

   Jun 2021 — Present · Los Angeles, CA, US

   As a Product Engineer at Luxima Technology, I lead the development, validation, and release of high-speed CMOS image sensor products used in automotive safety, wafer inspection, and medical imaging systems. I focus on ATE-compatible test infrastructure, wafer-level integration with OSAT partners, and test system bring-up — from design to volume manufacturing.Key contributions include:• Led NPI execution for 5+ CMOS image sensor products, owning package design for manufacturability, test plan development, assembly flow, and yield ramp strategy.• Engineered and deployed test sockets and mechanical fixtures for sensor validation, reducing test time by 85% and enabling streamlined integration into high-speed imaging systems.• Partnered with OSAT vendors to develop wafer probe and test infrastructure aligned with ATE platforms, resulting in $1.7M in annual cost savings through probe card optimization and process scrap reduction.• Executed RCCA and statistical analysis using MATLAB and SPC tools to identify yield loss trends, leading to >50% wafer yield improvement across multiple lines.• Collaborated with DFT and hardware teams to validate sensor test logic using JTAG and FPGA-based tools (Vivado ILA), supporting bring-up and debug during early product stages.• Built and deployed automated KPI monitoring tools in MATLAB to track key performance indicators (e.g, PRNU, SNR, image lag) in production.• Led DFM and DFT reviews, ensuring manufacturability and test compatibility across 5 semiconductor packaging configurations.• Supported global customers, fabs, and OSATs across the supply chain to align on test specs, quality gates, and manufacturing readiness.

Education

• University of Mumbai

  Bachelor of Engineering, Mechanical Engineering

• Michigan Technological University

  Master of Science - MS, Mechanical Engineering

  2019 — 2021