J. R. Petrus
Digital Verification Engineer at HRT
- Role
- Fpga Verification Engineer at Hudson River Trading
- Location
- Boulder, CO, US
- LinkedIn followers
- 500 followers
About J. R. Petrus
I am an FPGA/ASIC design and verification engineer. I specialize in packet processing, modeling and simulation platforms, and embedded systems.HDLs: VHDL, SystemVerilog & UVM, SystemC, Python, and cocotbTools: Cadence Xcelium, Mentor QuestaSim, Synplify, Xilinx ISE, Altera Quartus, and Cadence RTL CompilerTechnologies: multigigabit transceivers, high-speed memories (DDR and QDR), Flash, networking protocols, RISC-V
Experience
Fpga Verification Engineer
Mar 2023 — Present · Boulder, CO, US
Education
Lehigh University
BS, Computer Engineering
1997 — 2001
Lehigh University
MS, Computer Engineering
2001 — 2003
Skills
- Fpga
- Embedded Systems
- Verilog
- Vhdl
- Linux
- Simulations
- Quartus
- Systemc
- C++
- Modelsim
- Altera
- Computer Engineering
- C
- Xilinx
- Computer Architecture
- Rtl Design
- Tcl
- Simulation
- Ethernet
- Python
- Digital Signal Processors
- Field-Programmable Gate Arrays (Fpga)
- Cadence
- Debugging
- Systemverilog
- Hardware Architecture
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