J Bhavana

RTL Design Engineer @ Qualcomm | Bits Pilani

Role
Rtl Design Engineer at 高通
Location
Hyderabad, TG, IN
LinkedIn followers
500 followers

Experience

  1. Rtl Design Engineer

    高通

    Jul 2024 — Present · Bengaluru, IN

Education

  • Dav Public school

    10 CGPA

  • Central University of Karnataka

    Bachelor of Technology - BTech

    2018 — 2022

  • Birla Institute of Technology and Science, Pilani - Goa Campus

    Master of Engineering - MEng

    2022 — 2024

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J Bhavana — Rtl Design Engineer at 高通 in Hyderabad, TG, IN | Unifers