Abhinav Choudhary

About Abhinav Choudhary

My current work centers on SRAM reliability and sustainability within advanced memory systems. I am pursuing an M.Tech in ECE (VLSI & Embedded Systems) at where my thesis analyzes error behavior in SRAM arrays and evaluates ECC techniques with respect to energy, latency, and carbon impact. This involves modeling soft-error rates, multi-bit upset patterns, SRAM access energy, and ECC correction overheads, and integrating these into a framework that quantifies sustainability trade-offs for different memory protection strategies. The objective is to enable ECC selection that improves reliability while minimizing power, area, and long-term environmental cost.Technically, I work across RTL design, memory characterization, and ASIC flows, with exposure to SRAM circuit behavior and system-level memory evaluation. I have designed 6T bitcells, sense amplifiers, and small arrays in 65 nm, and implemented digital blocks such as UART controllers through full RTL-to-GDSII sign-off using both Cadence and open-source toolchains. I also contribute to ECC evaluation frameworks that integrate energy, latency, and FIT-based reliability metrics, and have validated layouts for tape-out.In parallel with memory-centric research, I have a strong interest in layout and physical design. I have worked with Virtuoso for device-level and custom layout, and used Innovus for floorplanning, placement, CTS, routing, and sign-off checks such as DRC/LVS, parasitic extraction, and STA. This dual focus on memory modeling and physical implementation allows me to evaluate SRAM subsystems from circuit, architectural, and physical perspectives, especially where layout choices influence read stability, bitline capacitance, leakage, and overall PPA.Overall, my thesis direction aligns with my broader interest in memory systems, low-power design, and physical implementation workflows that translate theoretical reliability and efficiency goals into silicon-accurate designs.

Experience

1. Intern

   铿腾设计系统公司

   Jan 2026 — Present · Noida, IN

   Developed a scalable shell-based automation framework to audit and extract Quantus CCL dependencies across a large golden regression tree under the xena-trans production environment. The tool canonicalizes paths, validates file existence, eliminates duplicates, and generates a consolidated, timestamped audit report of absolute CCL paths for regression traceability and validation consistency.This automation ensures visibility into command-level configuration usage across PV testcases, enabling systematic validation, dependency tracking, and configuration drift analysis in advanced node extraction flows.

Education

• Indraprastha Institute of Information Technology, Delhi

  Master's of Technology, MTech - VLSI & Embedded Systems

• Maharaja Agrasen Institute Of Technology, Delhi

  Bachelor's degree, Electrical and Electronics Engineering