Iteeshree Sinha

About Iteeshree Sinha

My expertise in Physical Design, Static Timing Analysis (STA), and Logic Synthesis has been instrumental in steering complex projects to successful tape-outs. My recent role at Intel as Lead Physical Design Engineer enriched my proficiency in Synthesis, Floorplan, Place and Route, and Physical Verification.With a focus on customer engagement and support, my contributions have fostered robust deployment strategies and innovative solutions. My adeptness in toolsets like Cadence Innovus and Synopsys PrimeTime, combined with my command of automation through Perl and TCL, has consistently delivered superior design quality and efficiency.

Experience

1. Senior Staff Physical Design Engineer

   IBM

   Jun 2024 — Present · IN

   IBM ISDL (Production Division)

Education

• Banasthali Vidyapith

  Diploma in medical image processing, Image processing

  2012 — 2013

• Centre for Development of Advanced Computing (C-DAC)

  Post Graduation diploma in VLSI design, VLSI design

  2015 — 2015

• Dr. A.P.J. Abdul Kalam Technical University

  Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering

  2006 — 2010

• Banasthali Vidyapith

  Master of Technology (M.Tech.), VLSI DESIGN

  2012 — 2014

Skills

• Android Sdk
• Matlab
• Cmos
• Vhdl
• Data Structures
• Layout Design
• Fpga
• Asic
• Field-Programmable Gate Arrays (Fpga)
• Integrated Circuit Design
• Functional Verification
• Object-Oriented Programming (Oop)
• Universal Verification Methodology (Uvm)
• Python
• C
• C++
• Verilog
• Application-Specific Integrated Circuits (Asic)
• Image Processing
• Perl
• Embedded Systems
• Semiconductors
• Semiconductor Device
• System Verilog
• Shell Scripting
• Very-Large-Scale Integration (Vlsi)
• Simulink
• Digital Design
• Systemverilog
• Cadence
• Vlsi