Mohammed Islam

About Mohammed Islam

Over 24 years’ experience of semiconductor design and Test methodology, implementation, verification and silicon validation on both block and full chip level.Drive DFT (Design for Testability) Technology, Develop and CAD support for DFT infrastructure. Define and Drive DFT standardization. Develop innovative DFT techniques and methodologies to improve product quality and reduced the test cost and timeArchitected, designed and validated DFT circuits including Stuck-at, At-speed Scan, Cell Aware, Power Aware ATPG, LBIST (Logic BIST), Memory BIST (MBIST) and Array Write Thru (AWT), Built in Self Repair (BISR) and Built in Redundancy Analysis (BIRA), Raster, Array Freeze and Array Debug. Specialty on RTL design, ATPG and EDT tool (Tetramax, Fastscan, TestCompress, DFTMax), Scan Chain insertion, Low Power ATPG, Core Based DFT (CBDFT), Modular Testing using Test Access Mechanism (TAM), Test-bench with functional verification, CAD tools, Logic verification tool and GLS (SHARK, VCS), Programming Languages (C/C++), Hardware description language (Verilog, System Verilog), Scripting language (Perl/TCL), assembly language (8086). Hands-on experience with silicon bring-up and debug on ATE (IMS Vanguard, NPTEST ST2, CMT and Microprocessor Failure Analysis (FA). Expertise on VLSI, Reliability, Circuit Simulation, and IC Layout.Experience and support DFT for High Speed IO like and SerDes, DDRPHY and USB 2.0/3.0.Very good communication skills, outstanding analytical and critical thinking skills, project management and customer orientation skills.

Experience

1. Principal Member of Technical Staff (Pmts) - Dft Atpg

   AMD

   Jun 2024 — Present

Education

• Rajshahi University, Bangladesh

  BS (Honors), Applied Physics & Electronics

  1992

• Rajshahi University, Bangladesh

  MS, Applied Physics & Electronics

  1993

• University of Central Florida

  MS; MS, EE; Physics

  1999 — 2001

Skills

• Static Timing Analysis
• Processors
• Ic
• Cmos
• Rtl Design
• Dft
• Veritas Cluster Server
• Primetime
• Formal Verification
• Very-Large-Scale Integration (Vlsi)
• Low-Power Design
• Soc
• Rtl Coding
• Systemverilog
• Atpg
• Timing Closure
• System on a Chip (Soc)
• Timing
• Physical Design
• Vlsi
• Debugging
• Silicon
• Functional Verification
• Spyglass
• Verilog
• Simulations
• Asic
• Logic Design
• Eda