Ishika Jain
SoC Logic Design Engineer @ Intel || MTech VLSI\'25
- Role
- Soc Logic Design Engineer at Intel
- Location
- Patiala, PB, IN
- LinkedIn followers
- 500 followers
About Ishika Jain
SoC Logic Design at Intel Corporation, responsible for performing Static Timing Analysis (STA) and Electrical Rule Checks (ERC) using Intel-specific tools, Synopsys Prime Time, and Fusion Compiler at the full-chip level for 3nm and 1.8nm technology nodes. Other responsibilities include the implementation of Engineering Change Orders (ECOs) on partitions of the SoC.MTech VLSI graduate, with an academic background in designing and implementing digital circuits.Experienced in working in a smart meter manufacturing industry, with a knowledge of Six Sigma and lean manufacturing.Consistently among the top 10 performers since the high school.With a passion for problem-solving and a commitment to continuous improvement, I am eager to contribute my skills and knowledge to drive success in a dynamic VLSI engineering role.
Experience
Soc Logic Design Engineer
Jun 2025 — Present · Bengaluru, IN
Education
Convent Of Jesus And Mary Dehradun
93.25
DIT UNIVERSITY
BTech - Bachelor of Technology
2018 — 2022
Thapar Institute of Engineering & Technology
Master of Technology - MTech
2023 — 2025
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