Indulakshmi V
Verfification Engineer at AMD
- Role
- Verification Engineer at AMD
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Indulakshmi V
Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models using Verilog HDL. Good experience in writing Test benches using SystemVerilog and UVM Very good knowledge in verification methodologies Experience in using industry standard EDA tools for the front-end design and verification
Experience
Verification Engineer
Sep 2022 — Present · Bengaluru, IN
Education
Anna University Chennai
M.E, VLSI Design
2016 — 2018
Maven Silicon
Trainee, Vlsi design and Verificatio
2019 — 2019
NEHRU COLLEGE OF ENGINEERING AND RESEARCH CENTRE, PAMBADY
Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering
2011 — 2015
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