Indu Prathapan
ASIC Design @Meta
- Role
- Asic Engineer, Design at Meta
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Indu Prathapan
Experience of 15+ years in the area of ASIC design for Signal Processing Cores, Hardware Accelerators and complex mixed-signal SoCs for WLAN PHY(802.11 a/b/g), FM baseband transceivers and Automotive Radar Systems.Architecture definition for ARM based CPU subsystems and CoreSight based Debug infrastructure for multi-core SoCs. Functional Safety solutions (ISO 26262) for Automotive IPs and SoCsWide-ranging hands-on experience in several domains of VLSI design flow spanning Microarchitecture definition, IP and SoC RTL, Interconnect architecture, AMBA protocols, Automotive and Industrial functional safety (FuSa), Multi-domain clocking, Low power design techniques, DV, Logic Synthesis, STA timing constraints, CDC, Complex ECOs and silicon debug with proven track record of on-time and quality execution.Focused on innovation. Holds 14 US patents and 6 publications
Experience
Asic Engineer, Design
Jul 2024 — Present
Education
University of Calicut
Bachelor of Engineering - BE, Electronics and Communications Engineering
1997 — 2001
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