Imtiaz Hussain

About Imtiaz Hussain

Over 20 years of experience in Logic Design, Physical Design and Post-Si Validation for high-performance and low power CPU designs + Defined and developed methodologies for applying automated solutions to solve timing convergence and routing congestion issues and power reduction in multi-GHz CPU designs+ Trained and mentored several engineers in the use of automated solutions and in coding techniques

Experience

1. Senior Validation Engineer

   Intel

   Jan 2012 — Present

   Emulation and post-Si debug and validation of low-power CPU designs, specifically on validation and debug of system power management features

Education

• Arizona State University

  MS, Electrical Engineering

  1997 — 1998

Skills

• Lvs
• Ic
• Static Timing Analysis
• Timing
• Verilog
• Soc
• System on a Chip (Soc)
• Eda
• Low-Power Design
• Logic Design
• Rtl Design
• Formal Verification
• Physical Design
• Processors
• Cmos
• Vlsi
• Compilers
• Logic Synthesis
• Place & Route
• Primetime
• Timing Closure
• Functional Verification
• Asic
• Dft
• Systemverilog
• Debugging
• Microprocessors