Imran Ahmed Khan
ASIC Verification Engineer | SystemVerilog | UVM
- Role
- Senior Validation Engineer at Intel Technologies India
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Imran Ahmed Khan
Around 8 Years of Experience in VLSI Verification1. Working on Constraint Driven Verification Environment.2. Developing the Testplans for the given specification3. Developing Verification Components like Driver, Monitor and Scoreboards4. Coding of sequences in UVM and Testcases in System Verilog.5. Implementation and Analysis of Functional coverage to reach 100%6. Running Nightly Regressions and debugging the failures7. Implementation of System Verilog Assertions with design signals and testbench variables, for the expected behavior of the Design.8. Holes analysis, improvement and exclusion for 100% Toggle Coverage
Experience
Senior Validation Engineer
Dec 2021 — Present · Hyderabad, IN
Education
JNTUH
Bachelor's degree, Electrical, Electronic and Communications Engineering Technology/Technician
2007 — 2011
K K High School
Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering
2007 — 2011
Skills
- Debugging
- Systemverilog
- System Verilog
- C
- Vlsi
- Open Verification Methodology
- Ncsim
- Soc
- Digital Electronics
- Perl Script
- Fpga
- Perl
- Embedded Systems
- Very-Large-Scale Integration (Vlsi)
- Veritas Cluster Server
- Microprocessors
- Verilog
- C++
- Pcie
- Functional Verification
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