Jayesh J Parmar

MTS Silicon Design Engineer

Role
Mts Silicon Design Engineer at AMD
Location
Bengaluru, KA, IN
LinkedIn followers
500 followers

About Jayesh J Parmar

Design & Verification EngineerI am a skilled Design & Verification Engineer, specializing in creating UVM and SV-based testbenches from scratch for IPs. My expertise includes everything from specifications to Test Plan creation, Verification Plan development, test case creation, sequence coding, coverage model generation, and System Verilog Assertions (SVA) implementation.I apply advanced verification strategies to identify design issues and bugs, enhancing the overall efficiency and robustness of RTL, while continuously improving the testbench quality.AI-based tools for automating verification workflows and improving the accuracy and speed of the verification process. Its not just word \"AI\" I do apply this into Hardware verification be it regression script,coverage,Formal and verification runs analysis and what not. Key Areas of Expertise :Experience in leading a team of 2-4 verification engineers to achieve project goals.Expertise in functional verification of IP, Modules & achieving optimal coverage.Experienced in Subsytem and SOC verification Formal Verification (Beginner) — applying formal methods to validate designs and ensure correctness.Experienced in Python and Tcl automation for DV and any requirements Tools & Technologies:Synopsys tools for comprehensive verification and simulation.Cadence Xcellium for efficient verification and coverage analysis.UVM and SystemVerilog for creating scalable and maintainable testbenches.Formal Verification tools for early-stage Design Verification.

Experience

  1. Mts Silicon Design Engineer

    AMD

    Apr 2024 — Present · Bengaluru, IN

Education

  • SILVER OAK UNIVERSITY

    Bachelor's degree, Electrical, Electronics and Communications Engineering Ahmedabad

    2013 — 2016

  • Nirma University

    Associate diploma, Electronic and Communications Engineering Technology Ahmedabad

    2010 — 2013

  • Gujarat Secondary and Higher Secondary Education Board (GSEB)

    High School, Business/Commerce, General

  • Gujarat Technological University (GTU)

    Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering

    2013 — 2016

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Jayesh J Parmar — Mts Silicon Design Engineer at AMD in Bengaluru, KA, IN | Unifers