Ismile Khan Shuvo
Process Development Engineer @Micron
- Role
- Process Development Engineer at Micron Technology
- Location
- Boise, ID, US
- LinkedIn followers
- 500 followers
About Ismile Khan Shuvo
Process Development Engineer with hands‑on experience in advanced DRAM and CMOS…
Experience
Process Development Engineer
Jun 2024 — Present · Boise, ID, US
As a Process Development Engineer in the 3D DRAM division at Micron, I contribute to the development and optimization of the thin film processes, with a focus on CVD and diffusion modules. My work supports the enablement of next-generation DRAM technologies through collaborative innovation, data-driven experimentation, and cross-functional alignment.Key highlights:• Lead process development for 2W Gap fill applications on oxide tools, supporting DRAM CMOS integration and yield improvement• As a Process and Step Owner Optimize Diffusion processes to reduce RPT & Cost to achieve process Goal and improve overall efficiency. This includes creating and refining recipes to ensure faster, cost efficient and high-quality production. • Develop new BKMs for Thin Films Deposition of Dielectrics using ALD, PEALD, Thermal growth and Treatment options for the creation and optimization of Hardmask Structures, High Aspect ratio Fills and Liners, and Thermal/Chemical Treatment of Substrates.• Engage in parametric testing and data analysis for DRAM lots, contributing to process control and device performance optimization• Contributed to offloading wafers by creating and optimizing oxide recipes to fill void free structure with different CD for 3DDRAM• Contributed to the reduction of Quality Defect reports (QDRs) by improving recipe and GDM setups which has led to reduce tool downtime and increased productivity• As a tool owner optimize Auto Clean setup to reduce particle and other metal contamination issues. • Improved process stability by reducing thickness drift due to drift in growth rate late in clean. • Created NAND/3DDRAM Equipment Group and Qual definition (with robust process) to have more tool time with successfully reducing Post Maintenance Qual time by half. • Used failure analysis, SPC/FDC methodology to identify, diagnose and resolve assembly process related problems
Education
Khulna University of Engineering and Technology
Bachelor's degree
2017 — 2022
University at Albany, SUNY
Nanoscale Engineering
2023 — 2028
Govt. City College,Chittagong
Science
2015 — 2016
P H Amin academy
Science
2010 — 2014
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