Igal Kupershlak

About Igal Kupershlak

Fully automated place & route flow development and implementation from RTL to GDS.TCL/PERL/cshell scripts – development and management.Physical Design CAD P&R tools – ICC, ICC2, FC, Cadence EDI, ATopTech(Aprisa), Mentor and others.UPF, low power design implementation.Development and management of IC BackEnd flow.Technology : 7n, 16n, 28n, 40n, 65n, 90n, 0.13u, 0.15u, 0.18u.Chip top level and sub macros Floorplanning.Support and development of CAD systems.Operating Systems: UNIX, LINUX, WindowsProgramming Languages: TCL, Perl, cshellSpecialties: Floorplanning, Timing driven place and route, Static Timing Analysis, Clock tree synthesys, DFT (scan) insertion,Logic Equivalence verification, Final Physical Verification(LVS/DRC),IR drop analysis.Perl/TCL/Cshel scripting.

Experience

1. Principal Physical Design Engineer

   Jariet Technologies

   Oct 2024 — Present · US

   Cadence Innovus flow implementation and development, Physical verification

Education

• Coventry University

  Bachelor’s Degree, Electrical and Electronics Engineering

  1997 — 2000

• Braude Academic College

  Engineer’s Degree, Electronics and Electrical Engineering Diploma

  1994 — 1996

Skills

• Ic Physical Design
• Static Timing Analysis
• Floorplanning
• Physical Design
• Timing
• Physical Verification
• Ic
• Dft
• Magma
• Place & Route
• Rtl
• Timing Closure
• Primetime
• Drc
• Lvs
• Clock Tree Synthesis
• Asic
• Tcl
• Cadence
• Perl
• Vlsi
• Logic Synthesis
• Signal Integrity