Ichrak Sadraoui
Master Thesis @STMicroelectronics
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WORK HISTORY
Master Thesis @STMicroelectronics
Currently working on the design, implementation, and testing of canary logic to detect timing violations caused by voltage glitch attacks targeting the secure enclave. The project involves RTL design in SystemVerilog, testbench development, functional simulation, specification definition, synthesis and timing analysis using 28nm FDSOI technology. It also includes preparing for backend implementation and running SPICE simulations on the hard macro to accurately model voltage glitch behavior.
EDUCATION
EPFL
Electrical and electronic engineering , Nanotechnology
Politecnico di Torino
Master of science program in nanotechnologies for integrated systems , Engineering
ABOUT ICHRAK SADRAOUI
As a highly motivated student with diverse international experiences, I am eager to learn and strive for meaningful achievements.My background has shaped a strong adaptability, curiosity, and collaborative mindset, supported by hands-on experience in nanotechnologies.
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