I Tara
Senior ASIC RTL Design Engineer | RTL Design | Verilog/VHDL/SV | LINT | CDC | Python/TCL Scripting | Microarchitecture | Digital Design | SOC Design & FEINT | IP/subsystem Design
- Role
- Senior Asic Rtl Design Engineer at HARMAN International
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About I Tara
I am a professional Senior ASIC RTL Design Engineer with over 5+ Years of Industrial Experience.Talk about #Verilog #VHDL #CDC #LINT #RTL Design and Integration #System Verilog #IP/sub-system Design #SOC Design #TCL scripting #ASIC Design
Experience
Senior Asic Rtl Design Engineer
Sep 2024 — Present · IN
Education
Aditya Educational Institutions
Bachelor of Technology - BTech, ECE
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