Huy Nguyen
Design Verification Engineer
- Role
- Design Verification Engineer at Meta
- Location
- Mountain View, CA, US
- LinkedIn followers
- 500 followers
About Huy Nguyen
Summary of Interest- SOC and IP testbench development and continuous functional verification methodology improvement Issued Patents:Monitoring coverage for static modeling of an electronic device, USPTO patent #91•••26Correlation of test results and test coverage for an electronic device design, USPTO patent #94•••89Static modeling of an electronic device, USPTO patent #10••••86Publications:\"Sequential equivalence checking of hard instances with targeted inductive invariants and efficient filtering strategies\", first author, HLDVT 2012 filtering of invariants for Sequential Equivalence Checking\", co-author, HLDVT 2011
Experience
Design Verification Engineer
Apr 2024 — Present · Sunnyvale, CA, US
Education
University of South Alabama
BS, Computer Engineering
2005 — 2008
Virginia Tech
Master, Computer Engineering
2009 — 2011
Skills
- Data Mining
- Computer Engineering
- Systemverilog
- Rtl Design
- Ifv
- Qt
- C++
- Vcs
- C
- Soc
- Python
- Verilog
- Uvm
- Formal Verification
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