Hussain Neralwala
ASIC RTL Design Lead at Google
- Role
- Asic Rtl Design Lead at Google
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Hussain Neralwala
Have worked multiple times across the SOC chip cycle starting from micro-architecture to RTL design, simulation, synthesis, STA, silicon bring-up, characterization, and final support for the SW, QA teams.
Experience
Asic Rtl Design Lead
Oct 2022 — Present · Bengaluru, IN
Education
Indian Institute of Technology, Bombay
M Tech, Systems and Control Engineering
2008 — 2010
University of Mumbai
Bachelors, Electronics and Telecommunication
2004 — 2008
Don Bosco Institute of technology
B.E., EXTC
2004 — 2008
Skills
- Cdc (Mentor Graphics)
- Verilog
- Fpga
- Embedded Systems
- Rtl Design
- Dsp
- Synopsys Tools
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